职位描述

招聘人数：3 人

职位职责： 实习天数：4 天 / 周

职位描述： 
1.负责数字IC设计的前端流程，包括 RTL design, verification, synthesis, timing analysis, DFT.参与后端流程，比如CTS, SI, Place & Routing, timing closure等。 
2.熟练使用Verilog及其他硬件设计语言。搭建仿真环境，验证模块及芯片功能。 
3.负责参与后仿验证，参与测试向量生成。 

任职要求： 
1.电子、微电子学或计算机专业本科以上学历 
2.熟练使用相关EDA软件,比如Synopsis, Cadence, NC-Verilog, VCS, DC/PT and ICC 
3.有无线SOC芯片项目经历,,有WIFI/BT/FM项目经验优先考虑。 
4.有很强的团队合作精神 
5.有汇编编程经验优先考虑 
6.有系统级FPGA , debug经验，熟悉常用FPGA芯片及相关软件。 

Job Description: 
1.Responsible for full design flow from RTL to netlist for physical/backend designer, including RTL design, verification, synthesis, timing analysis, DFT. Participate in Floorplan, CTS, SI, Place & Routing, timing closure and etc. 
2.Testbench generation, module/chip (or system) level verifications using Verilog or other verification languages. 
3.Participate in test pattern generation, backend verification and layout review. 

Requirement: 
1. Bachelor, Master or above in Electronic, Microelectronics Engineering and Computer Science. 
2. Familiar with EDA tools from Synopsis, Cadence, like NC-Verilog, VCS, DC/PT and ICC 
3. Experience in communication soc chip projects, Experiences of wireless SOC chips, especially Bluetooth SoC and/or wifi SOC (NOT must), are highly appreciated. 
4. Good team work spirit, easy to cooperate with team members. 
5. Experience of assemble language are highly appreciated. 
6.Strong logic design and verification/debugging skills. 
7.Be familiar with chip level integration and debugging with FPGA