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职位描述
GPU ASIC Physical Design engineer As a senior member of our ASIC-PD team, youll be working on streamlining the chip infrastructure process across product designs, focusing on full chip layout planning (partitioning, planning clock distribution and other structure, methodology), partition/full chip timing closure (primetime scripts, other tools, etc) and gate-level design of high-speed logic RESPONSIBILITIES: Chip integration and netlist generation -Synthesis, Formal verification, netlist quality check Work in conjunction with Place and Route Engineers to achieve timing closure for both partition level and full chip level Develop and enhance entire timing flow from frontend (pre-layout) to backend (post-layout) at both chip and block level. Develop custom timing scripts using tcl/primetime for clock skew analysis, special circuits such as clock dividers, core logic IO macros interfaces such as PCI-E, Frame-Buffer/Memory, TMDS, etc. Develop flow to physically partition and floorplan the entire chip. Develop scripts for performing ECOs. MINIMUM REQUIREMENTS: BS or MS in Electrical Engineering or Computer Science Above 3 years of relevant ASIC experience ideally with a focus in the chip integration /synthesis/formal and timing closure - Excellent scripts skills - Excellent written and verbal communication skills in English - Ability to multiplex many issues, set priorities, and work in a team environment - Keep up to date with leading edge technologies
工作地点
上海 收起地图@2008-2023 大街网 京ICP备09028813号-1 人才服务许可证:1101052019005号 电子营业执照 京公网安备 11010802034037号 京ICP证090373号
北京大杰致远信息技术有限公司 公司地址:北京市海淀区成府路28号优盛大厦D座18层1801 联系邮箱:service@dajie.com 联系电话:4006371088(工作时间)