GPU ASIC Physical Design engineer
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  • 全职
  • |
  • 上海
  • |
  • 若干
  • |
  • 1年及以上工作经验
  • |
  • 本科及以上
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NVIDIA英伟达 Recruiter

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职位描述

  • 电子技术/半导体/集成电路行业
  • 软件研发
招聘人数:若干

                    职位职责:

                    
GPU ASIC Physical Design engineer
As a senior member of our ASIC-PD team, youll be working on streamlining the chip infrastructure process across product designs, focusing on full chip layout planning (partitioning, planning clock distribution and other structure, methodology), partition/full chip timing closure (primetime scripts, other tools, etc) and gate-level design of high-speed logic

RESPONSIBILITIES:
Chip integration and netlist generation
-Synthesis, Formal verification, netlist quality check
Work in conjunction with Place and Route Engineers to achieve timing closure for both partition level and full chip level
Develop and enhance entire timing flow from frontend (pre-layout) to backend (post-layout) at both chip and block level.
Develop custom timing scripts using tcl/primetime for clock skew analysis, special circuits such as clock dividers, core logic  IO macros interfaces such as PCI-E, Frame-Buffer/Memory, TMDS, etc.
Develop flow to physically partition and floorplan the entire chip.
Develop scripts for performing ECOs.

MINIMUM REQUIREMENTS:
BS or MS in Electrical Engineering or Computer Science
Above 3 years of relevant ASIC experience ideally with a focus in the chip integration /synthesis/formal and timing closure
- Excellent scripts skills
- Excellent written and verbal communication skills in English
- Ability to multiplex many issues, set priorities, and work in a team environment
- Keep up to date with leading edge technologies

工作地点

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NVIDIA英伟达